Miniaturization has been the basis of tremendous success in the semiconductor industry. To continue downsizing, however, innovative methods are required to overcome new challenges. For example, as semiconductor wafers become smaller, it is more important to isolate and direct electrical charges to avoid interference. One solution is silicon-on-insulator (“SOI”) technology. SOI technology is a semiconductor fabrication technique perfected by IBM that uses pure crystal silicon and silicon oxide for integrated circuits and microchips. G. Shahidi, SOI Technology for the GHz Era, IBM J. RES. & DEV., 46:2/3, 121-131 (2002). An “SOI” wafer is, for example, a wafer wherein a layer of buried oxide (“BOX”) is implanted between two sides of a semiconductor substance. Most SOI wafers are fabricated by use of one of two basic approaches. SOI wafers may be fabricated with the SIMOX™ (Separation by Implanted Oxygen) process, which employs high dose ion implantation of oxygen and high temperature annealing to form the BOX layer in a bulk wafer. Alternatively, SOI wafers can be fabricated by bonding a device quality silicon wafer to another silicon wafer that has an oxide layer on its surface. The pair is then split apart, using a process that leaves a thin (relative to the thickness of the starting wafer) device-quality layer of single crystal silicon on top of the oxide layer. This is called the “layer transfer” technique, because it transfers a thin layer of device-quality silicon onto an oxide layer that was thermally grown on a wafer. An SOI wafer has a buried oxide layer typically less than 100 nm thick. This oxide layers acts as an insulator to stop unwanted electrical loss. The amount of electrical charge the transistor has to move during a switching operation is reduced making it faster and allowing it to switch using less energy. SOI wafers can provide a 20-35% performance gain over bulk complementary metal-oxide semiconductor (“CMOS”) based chips. G. Shahidi, SOI Technology for the GHz Era, IBM J. RES. & DEV., 46:2/3, 121-131 (2002). Also, SOI chips reduce the soft error rate, which is data corruption caused by cosmic rays and natural radioactive background signals. As miniaturization continues, SOI is expected to be the technology of choice for system-on-a-chip applications which require high-performance CMOS, low-power, embedded memory, and bipolar devices.
High performance CMOS devices increasingly incorporate high-k gate dielectrics and metal gates. In the fabrication of metal gates, the conventional approach has been subtractive, i.e., the metal gate material is applied as a blanket layer and then selectively removed from regions where it is not wanted. For example, when electrodeposition technique is used for fabrication of metal structures on dielectrics, the electrodeposited metal is nearly always deposited on a metallic seed or plating base layer formed on a substrate by a method other than electrodeposition (e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), etc.). The main path for the current flow driving the electrodeposition is laterally through the seed layer, from contact established at the seed layer edges. Current through the substrate itself, and any dielectric layers contained therein, is typically completely negligible. Plating can be limited to selected areas of the seed layer by using though-mask plating techniques, wherein one plates through the openings in an insulating masking layer disposed directly on the seed layer. So for metal gate application, the gate metal may be selectively deposited on the desired gate regions by through-mask plating onto a blanket conductive seed layer, which would typically be removed from the masked regions after the plating process. Gates for n-FET and p-FET devices have different work functions and comprise different metals, which mean that the additive through-mask plating approach must be done more than once. An electrodeposition approach is described as an additive method for forming metal gates for field effect transistors in U.S. Patent Application Publication No. 20050095852 entitled “Field Effect Transistor with Electroplated Metal Gate,” the entire disclosure of which is incorporated herein by reference. Methods of electrodeposition are provided in U.S. Patent Application Publication No. 20060166474, which is also incorporated herein by reference in its entirety. These publications show electroplating metal on resistive substrates for various applications using backside contact so that the wafer is used as the source of electrons for the electroplating process.